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september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion flash memory data sheet tm
ds05-20860-6e fujitsu semiconductor data sheet flash memory cmos 8m (1m 8 / 512k 16) bit mbm29dl800ta -70/90 /mbm29dl800ba -70/90 n features ? single 3.0 v read, program, and erase minimizes system level power requirements ? simultaneous operations read-while-erase or read-while-program ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard worldwide pinouts (pin compatible with mbm29lv800ta/ba) 48-pin tsop(1) (package suffix: pftn C normal bend type, pftr C reversed bend type) 48-ball fbga (package suffix: pbt) ? minimum 100,000 program/erase cycles ? high performance 70 ns maximum access time ? sector erase architecture two 16 k byte, four 8 k bytes, two 32 k byte, and fourteen 64 k bytes. any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture t = top sector b = bottom sector ? embedded erase tm algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ?low v cc write inhibit 2.5 v ? erase suspend/resume suspends the erase operation to allow a read in another sector within the same device (continued) embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 2 (continued) ? sector protection hardware method disables any combination of sectors from program or erase operations ? sector protection set function by extended sector protection command ? fast programming function by extended command ? temporary sector unprotection temporary sector unprotection via the reset pin. n packages 48-pin plastic tsop (i) (fpt-48p-m19) 48-pin plastic tsop (i) (fpt-48p-m20) marking side marking side 48-pin plastic fbga (bga-48p-m12)
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 3 n general description the mbm29dl800ta/ba are a 8m-bit, 3.0 v-only flash memory organized as 1 m bytes of 8 bits each or 512 k words of 16 bits each. the mbm29dl800ta/ba are offered in a 48-pin tsop(1) and 48-ball fbga packages. these devices are designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. mbm29dl800ta/ba provide simultaneous operation which can read a data during program/erase. the simultaneous operation architecture provides simultaneous operation by dividing the memory space into two banks. the device can allow a host system to program or erase in one bank, then immediately and simultaneously read from the other bank. the standard mbm29dl800ta/ba offer access times 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the devices have separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29dl800ta/ba are pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the devices is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29dl800ta/ba are programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the devices automatically time the erase pulse widths and verify proper cell margin. a sector is typically erased and verified in 1.0 second. (if already completely preprogrammed.) the devices also feature a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29dl800ta/ba are erased when shipped from the factory. the devices feature single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. fujitsus flash technology combines years of eprom and e2prom experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm29dl800ta/ba memories electrically erase the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 4 n n n n product line up n block diagram part no. mbm29dl800ta/mbm29dl800ba ordering part no. v cc = 3.3 v -70 v cc = 3.0 v -90 max address access time (ns) 70 90 max ce access time (ns) 70 90 max oe access time (ns) 30 35 v ss v cc bank 2 address bank 1 address we ce a 0 to a 18 (a -1 ) oe byte reset dq 0 to dq 15 ry/by state control command register x-decoder x-decoder cell matrix (bank 2) cell matrix (bank 1) y-gating & data latch y-gating & data latch dq 0 to dq 15 status +0.3 v C0.3 v +0.6 v C0.3 v
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 5 n pin assignments (continued) a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 n.c. n.c. we reset n.c. n.c. ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mbm29dl800ta/mbm29dl800ba normal bend mbm29dl800ta/mbm29dl800ba reverse bend tsop(1) a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a -1 v ss byte a 16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 ry/by n.c. n.c. reset we n.c. n.c. a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 (marking side) (marking side) (fpt-48p-m19) (fpt-48p-m20)
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 6 (continued) a3 a1 a2 a6 a5 b1 b2 b3 b4 b5 b6 c1 c2 c3 c4 c5 c6 d1 d2 d3 d4 d5 d6 e1 e2 e3 e4 e5 e6 f1 f2 f3 f4 f5 f6 g1 g2 g3 g4 g5 g6 h1 h2 h3 h4 h5 h6 (top view) marking side fbga a4 a1 a 3 a2 a 7 a3 ry/by a4 we a5 a 9 a6 a 13 b1 a 4 b2 a 17 b3 n.c. b4 reset b5 a 8 b6 a 12 c1 a 2 c2 a 6 c3 a 18 c4 n.c. c5 a 10 c6 a 14 d1 a 1 d2 a 5 d3 n.c. d4 n.c. d5 a 11 d6 a 15 e1 a 0 e2 dq 0 e3 dq 2 e4 dq 5 e5 dq 7 e6 a 16 f1 ce f2 dq 8 f3 dq 10 f4 dq 12 f5 dq 14 f6 byte g1 oe g2 dq 9 g3 dq 11 g4 v cc g5 dq 13 g6 dq 15 /a -1 h1 v ss h2 dq 1 h3 dq 3 h4 dq 4 h5 dq 6 h6 v ss (bga-48p-m12)
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 7 n n n n pin description n n n n logic symbol pin name function a -1 , a 0 to a 18 address inputs dq 0 to dq 15 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector unprotection byte selects 8-bit or 16-bit mode n.c. no internal connection v ss device ground v cc device power supply 19 a 0 to a 18 we oe ce dq 0 to dq 15 16 or 8 byte reset a -1 ry/by
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 8 n n n n device bus operation legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. *1 : manufacturer and device codes may also be accessed via a command register write sequence. see mbm29dl800ta/ba command definitions table. *2 : refer to the section on sector protection. *3 : we can be v il if oe is v il , oe at v ih initiates the write operations. *4 : v cc = 3.0 v 10% *5 : it is also used for the extended sector protection. mbm29dl800ta/ba user bus operations table (byte = v ih ) operation ce oe we a 0 a 1 a 6 a 9 dq 0 to dq 15 reset auto-select manufacturer code* 1 llhlllv id code h auto-select device code* 1 llhhllv id code h read* 3 llha 0 a 1 a 6 a 9 d out h standby hxxxxxx high-z h output disable lhhxxxx high-z h write (program/erase) l h l a 0 a 1 a 6 a 9 d in h enable sector protection* 2 , * 4 lv id lhlv id xh verify sector protection * 2 , * 4 llhlhlv id code h temporary sector unprotection* 5 xxxxxxx x v id reset (hardware)/standby xxxxxxx high-z l mbm29dl800ta/ba user bus operations table (byte = v il ) operation ce oe we dq 15 / a -1 a 0 a 1 a 6 a 9 dq 0 to dq 7 reset auto-select manufacturer code* 1 llhllllv id code h auto-select device code* 1 llhlhllv id code h read* 3 llha -1 a 0 a 1 a 6 a 9 d out h standby h x x x xxxxhigh-z h output disable lhhxxxxxhigh-z h write (program/erase) l h l a -1 a 0 a 1 a 6 a 9 d in h enable sector protection* 2 , * 4 lv id llhlv id xh verify sector protection * 2 , * 4 llhllhlv id code h temporary sector unprotection * 5 xxxxxxxx x v id reset (hardware)/standby xxxxxxxxhigh-z l
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 9 *1 : this command is valid during fast mode. *2 : this command is valid while reset =v id . *3 : this data 00h is also acceptable. notes : address bits a 12 to a 18 = x = h or l for all address commands except or program address (pa), sector address (sa), and bank address (ba). bus operations are defined in mbm29dl800ta/ba user bus operations tables (byte = v ih and byte = v il ). ra =address of the memory location to be read pa =address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa =address of the sector to be erased. the combination of a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba =bank address (a 16 to a 18 ) rd =data read from location ra during read operation. pd =data to be programmed at location pa. data is latched on the rising edge of write pulse. spa =sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd =sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 0 to a 11 byte mode: aaah or 555h to addresses a C1 and a 0 to a 11 both read/reset commands are functionally equivalent, resetting the device to the read mode. the command combinations not described in mbm29dl800ta/ba command definitions table are illegal. mbm29dl800ta/ba command definitions table command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset word 1 xxxh f0h byte read/reset word 3 555h aah 2aah 55h 555h f0hrard byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h (ba) 555h 90h byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0hpapd byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h erase suspend 1 ba b0h erase resume 1 ba30h set to fast mode word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program * 1 word 2 xxxh a0hpapd byte xxxh reset from fast mode * 1 word 2 ba 90h xxxh f0h * 3 byte ba xxxh extended sector protect* 2 word 4 xxxh 60h spa 60h spa 40h spa sd byte
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 10 *1 : a -1 is for byte mode. at byte mode, dq 8 to dq 14 are high-z and dq 15 is a -1 , the lowest address. *2 : outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. (b): byte mode (w): word mode hi-z: high-z * : at byte mode, dq 8 to dq 14 are high-z and dq 15 is a- 1 , the lowest address. mbm29dl800ta/ba sector protection verify autoselect codes table type a 12 to a 18 a 6 a 1 a 0 a -1 *1 code (hex) manufactures code x v il v il v il v il 04h device code mbm29dl800ta byte xv il v il v ih v il 4ah word x 224ah mbm29dl800ba byte xv il v il v ih v il cbh word x 22cbh sector protection sector addresses v il v ih v il v il 01h *2 extended autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h a -1 /0 000000000 000100 device code mbm29dl800ta (b)* 4ah a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01001010 (w) 224ah 0010001001 001010 mbm29dl800ba (b)* cbh a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 11001011 (w) 22cbh 0010001011 001011 sector protection 01h a -1 /0 000000000 000001
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 11 n n n n flexible sector-erase architecture ? two 16 k bytes, four 8 k bytes, two 32 k bytes, and fourteen 64 k bytes ? individual-sector, multiple-sector, or bulk-erase capability ? individual or multiple-sector protection is user definable. 16 k byte 32 k byte 8 k byte 8 k byte 8 k byte 8 k byte 32 k byte 16 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 7ffffh 7dfffh 79fffh 78fffh 77fffh 76fffh 75fffh 71fffh 6ffffh 67fffh 5ffffh 57fffh 4ffffh 47fffh 3ffffh 37fffh 2ffffh 27fffh 1ffffh 17fffh 0ffffh 07fffh 00000h fffffh fbfffh f3fffh f1fffh effffh edfffh ebfffh e3fffh dffffh cffffh bffffh affffh 9ffffh 8ffffh 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh 00000h 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 64 k byte 16 k byte 32 k byte 8 k byte 8 k byte 8 k byte 8 k byte 32 k byte 16 k byte fffffh effffh dffffh cffffh bffffh affffh 9ffffh 8ffffh 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 1bfffh 13fffh 11fffh 0ffffh 0dfffh 0bfffh 03fffh 00000h 7ffffh 77fffh 6ffffh 67fffh 5ffffh 57fffh 4ffffh 47fffh 3ffffh 37fffh 2ffffh 27fffh 1ffffh 17fffh 0ffffh 0dfffh 09fffh 08fffh 07fffh 06fffh 05fffh 01fffh 00000h mbm29dl800ta sector architecture mbm29dl800ba sector architecture ( 16) ( 8) ( 16) ( 8) bank 2 bank 1 bank 2 bank 1
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 12 note : the address range is a 18 : a -1 if in byte mode (byte = v il ). the address range is a 18 : a 0 if in word mode (byte = v ih ). sector address table (mbm29dl800ba) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa211111xxx 64/32 f0000h to fffffh780 00h to 7ffffh sa201110xxx 64/32 e00 00h to effffh 70000h to 77fffh sa191101xxx 64/32 d0000h to dffffh680 00h to 6ffffh sa181100xxx 64/32 c0000h to cffffh600 00h to 67fffh sa171011xxx 64/32 b00 00h to bffffh 58000h to 5ffffh sa161010xxx 64/32 a00 00h to affffh 50000h to 57fffh sa151001xxx 64/32 900 00h to 9ffffh 48000h to 4ffffh sa141000xxx 64/32 800 00h to 8ffffh 40000h to 47fffh sa130111xxx 64/32 700 00h to 7ffffh 38000h to 3ffffh sa120110xxx 64/32 600 00h to 6ffffh 30000h to 37fffh sa110101xxx 64/32 500 00h to 5ffffh 28000h to 2ffffh sa100100xxx 64/32 400 00h to 4ffffh 20000h to 27fffh sa9 0011xxx 64/32 300 00h to 3ffffh 18000h to 1ffffh sa8 0010xxx 64/32 200 00h to 2ffffh 10000h to 17fffh bank 1 sa7 000111x 16/8 1c000h to 1ffffh0e 000h to 0ffffh sa6 0001 10x 32/16 18000h to 1bfffh, 14000h to 17fffh 0c000h to 0dfffh, 0a000h to 0bfffh 01x sa5 0001001 8/4 12 000h to 13fffh 09000h to 09fffh sa4 0001000 8/4 10 000h to 11fffh 08000h to 08fffh sa3 0000111 8/4 0e 000h to 0ffffh 07000h to 07fffh sa2 0000110 8/4 0c 000h to 0dfffh 06000h to 06fffh sa1 0000 10x 32/16 08000h to 0bfffh, 04000h to 07fffh 04000h to 05fffh, 02000h to 03fffh 01x sa0 000000x 16/8 00 000h to 03fffh 00000h to 01fffh
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 13 note : the address range is a 18 : a -1 if in byte mode (byte = v il ). the address range is a 18 : a 0 if in word mode (byte = v ih ). sector address table (mbm29dl800ta) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 0000xxx 64/32 000 00h to 0ffffh 00000h to 07fffh sa1 0001xxx 64/32 100 00h to 1ffffh 08000h to 0ffffh sa2 0010xxx 64/32 200 00h to 2ffffh 10000h to 17fffh sa3 0011xxx 64/32 300 00h to 3ffffh 18000h to 1ffffh sa4 0100xxx 64/32 400 00h to 4ffffh 20000h to 27fffh sa5 0101xxx 64/32 500 00h to 5ffffh 28000h to 2ffffh sa6 0110xxx 64/32 600 00h to 6ffffh 30000h to 37fffh sa7 0111xxx 64/32 700 00h to 7ffffh 38000h to 3ffffh sa8 1000xxx 64/32 800 00h to 8ffffh 40000h to 47fffh sa9 1001xxx 64/32 900 00h to 9ffffh 48000h to 4ffffh sa101010xxx 64/32 a00 00h to affffh 50000h to 57fffh sa111011xxx 64/32 b00 00h to bffffh 58000h to 5ffffh sa121100xxx 64/32 c0000h to cffffh600 00h to 67fffh sa131101xxx 64/32 d0000h to dffffh680 00h to 6ffffh bank 1 sa14111000x 16/8 e0 000h to e3fffh 70000h to 71fffh sa151110 01x 32/16 e4000h to e7fffh, e8000h to ebfffh 72000h to 73fffh, 74000h to 75fffh 10x sa161110110 8/4 ec 000h to edfffh 76000h to 76fffh sa171110111 8/4 ee 000h to effffh 77000h to 77fffh sa181111000 8/4 f0 000h to f1fffh 78000h to 78fffh sa191111001 8/4 f2 000h to f3fffh 79000h to 79fffh sa201111 01x 32/16 f4000h to f7fffh, f8000h to fbfffh 7a000h to 7bfffh, 7c000h to 7dfffh 10x sa21111111x 16/8 fc000h to fffffh7e 000h to 7ffffh
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 14 n n n n functional description simultaneous operation mbm29dl800ta/ba have feature, which is capability of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program). the bank selection can be selected by bank address (a 16 to a 18 ) with zero latency. the mbm29dl800ta/ba have two banks which contain bank 1 (16 kb, 32 kb, 8 kb, 8 kb, 8 kb, 8 kb, 32 kb, and 16 kb) and bank 2 (64 kb fourteen sectors). the simultaneous operation can not execute multi-function mode in the same bank. simultaneous operation table shows combination to be possible for simultaneous operation. *: an erase operation may also be supended to read from or program to a sector not being erased. read mode the mbm29dl800ta/ba have two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change ce pin from h or l standby mode there are two ways to implement the standby mode on the mbm29dl800ta/ba devices, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a max during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l). under this condition the current is consumed is less than 5 m a max once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. simultaneous operation table case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 15 automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29dl800ta/ba data. this mode can be used effectively with an application requested low power consumption such as handy terminals. to activate this mode, mbm29dl800ta/ba automatically switch themselves to low power mode when mbm29dl800ta/ba addresses remain stably during access fine of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 m a (cmos level). during simultaneous operation, v cc active current (i cc2 ) is required. since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically and mbm29dl800ta/ba read-out the data for changed addresses. output disable with the oe input at a logic high level (v ih ), output from the devices are disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the devices. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , and a 6 (a -1 ). (see mbm29dl800ta/ba user bus operations ta b l e s ( b y t e = v ih and byte = v il ) in n device bus operation.) the manufacturer and device codes may also be read via the command register, for instances when the mbm29dl800ta/ba are erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in mbm29dl800ta/ba command definitions table (in n device bus operation). (refer to autoselect command section.) word 0 (a 0 = v il ) represents the manufacturers code (fujitsu = 04h) and word 1 (a 0 = v ih ) represents the device identifier code (mbm29dl800ta = 4ah and mbm29dl800ba = cbh for 8 mode; mbm29dl800ta = 224ah and mbm29dl800ba = 22cbh for 16 mode). these two bytes/words are given in mbm29dl800ta/ba sector protection verify autoselect codes table and extended autoselect code table (in n device bus operation). all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see mbm29dl800ta/ba sector protection verify autoselect codes table and extended autoselect code table in n device bus operation.) in case of applying v id on a 9 , since both bank 1 and bank 2 enters autoselect mode, the simultenous operation can not be executed. write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 16 sector protection the mbm29dl800ta/ba feature hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 21). the sector protection feature is enabled using programming equipment at the users site. the devices are shipped with all sectors unprotected. alternatively, fujitsu may program and protect sectors in the factory prior to shiping the device. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il , and a 0 = a 6 = v il , a 1 = v ih . the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. sector address tables (mbm29dl800ta/ba) in n flexible sector-erase architecture define the sector address for each of the twenty two (22) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see (13) ac waveforms for sector protection in n timing diagram and (5) sector protection algorithm in n flow chart for sector protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the devices will read 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to apply to v il on byte mode. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector address will produce a logical 1 at dq 0 for a protected sector. see mbm29dl800ta/ba sector protection verify autoselect codes table and extended autoselect code table in n device bus operation for autoselect codes. temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the mbm29dl800ta/ba devices in order to change data. the sector unprotection mode is activated by setting the reset pin to high voltage (12 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the 12 v is taken away from the reset pin, all the previously protected sectors will be protected again. see (14) temporary sector unprotection timing diagram in n timing diagram and (6) temporary sector unprotection algorithm in n flow chart. reset hardware reset the mbm29dl800ta/ba devices may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least 500 ns in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode 20 m s after the reset pin is driven low. furthermore, once the reset pin goes high, the devices require an additional t rh before it will allow read access. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see (9) reset /ry/by timing diagram in n timing diagram for the timing diagram. refer to temporary sector unprotection for additional functionality.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 17 n n n n command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the devices to the read mode. some commands are required bank address (ba) input. when command sequences are inputed to bank being read, the commands have priority than reading. mbm29dl800ta/ba command definitions table in n device bus operation defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 0 to dq 7 and dq 8 to dq 15 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/ reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the devices remain enabled for reads until the command register contents are altered. the devices will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the devices reside in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address (ba) and the autoselect command. then the manufacture and device codes can be read from the bank, and an actual data of memory cell can be read from the another bank. following the command write, a read cycle from address (ba)00h retrieves the manufacture code of 04h. a read cycle from address (ba)01h for 16((ba)02h for 8) returns the device code (mbm29dl800ta = 4ah and mbm29dl800ba = cbh for 8 mode; mbm29dl800ta = 224ah and mbm29dl800ba = 22cbh for 16 mode). (see mbm29dl800ta/ba sector protection verify autoselect codes table and extended autoselect code ta b l e i n n device bus operation.) all manufacturer and device codes will exhibit odd parity with dq 7 defined as the parity bit. sector state (protection or unprotection) will be informed by address (ba)02h for 16 ((ba)04h for 8). scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. the programming verification should be performed by verify sector protection on the protected sector. (see mbm29dl800ta/ba user bus operations tables (byte = v ih and byte = v il ) in n device bus operation.) the manufacture and device codes can be allowed reading from selected bank. to read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write read/reset command sequence into the register and then autoselect command should be written into the bank to be read. if the software (program code) for autoselect command is stored into the frash memory, the device and manufacture codes should be read from the other bank where is not contain the software.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 18 to terminate the operation, it is necessary to write the read/reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing read/reset command sequence. byte/word programming the devices are programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the data polling and toggle bit must be performed at the memory location which is being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (see hardware sequence flags table.) therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. (1) embedded program tm algorithm in n flow chart illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read the mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) (2) embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 19 sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we whichever happens later, while the command (data=30h) is latched on the rising edge of ce or we which happens first. after time-out of 50 m s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on mbm29dl800ta/ba command definitions table in n device bus operation. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 s otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 m s from the rising edge of last ce or we whichever happens first will initiate the execution of the sector erase command(s). if another falling edge of ce or we , whichever happens first occurs within the 50 m s time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. resetting the devices once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 21). sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the sector erase begins after the 50 m s time out from the rising edge of ce or we whichever happens first for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the devices return to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector erase time + sector program time (preprogramming)] number of sector erase in case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe. (2) embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the bank addresses of sector being erasing or suspending should be set when writting the erase suspend or erase resume command.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 20 when the erase suspend command is written during the sector erase operation, the device will take a maximum of 20 m s to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/ by output pin will be at hi-z and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address within bank being erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written to the bank being erase suspended. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. extended command (1) fast mode mbm29dl800ta/ba has fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. the first cycle must contain the bank address. (refer to (8) embedded program tm algorithm for fast mode in n flow chart extended algorithm.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to (8) embedded program tm algorithm for fast mode in n flow chart extended algorithm.) (3) extended sector protection in addition to normal sector protection, the mbm29dl800ta/ba has extended sector protection as extended function. this function enable to protect sector by forcing v id on reset pin and write a commnad sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector protection in this mode. the extended sector protect requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector addresses pins (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to the sector to be protected (recommend to set v il for the other addresses pins), and write extended sector protect command (60h). a sector is typically protected in 250 m s. to verify programming of the protection circuitry, the sector addresses pins (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h). following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, please repeat to write extended sector protect command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih .
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 21 write operation status detailed in hardware sequence flags table are all the status flags that can determine the status of the bank for the current mode operation. the read operation from the bank where is not operate embedded algorithm returns a data of memory cell. these bits offer a method for determining whether a embedded algorithm is completed properly. the information on dq 2 is address sensitive. this means that if an address from an erasing sector is consectively read, then the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non- erasing sector is consectively read. this allows the user to determine which sectors are erasing and which are not. the status flag is not output from bank (non-busy bank) not executing embedded algorithm. for example, there is bank (busy bank) which is now executing embedded algorithm. when the read sequence is [1] , [2] , [3] , the dq 6 is toggling in the case of [1] and [3]. in case of [2], the data of memory cell is outputted. in the erase-suspend read mode with the same read sequence, dq 6 will not be toggled in the [1] and [3]. in the erase suspend read mode, dq 2 is toggled in the [1] and [3]. in case of [2], the data of memory cell is outputted. *1 : successive reads from the erasing or erase-suspend sector cause dq 2 to toggle. *2 : reading from non-erase suspend sector address indicates logic 1 at the dq 2 bit. hardware sequence flags table status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle* 1 erase suspended mode erase suspend read (erase suspended sector) 1100toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle 0 0 1* 2 exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 22 dq 7 data polling the mbm29dl800ta/ba devices feature data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the devices will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in (3) data polling algorithm in n flow chart. for programming, the data polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. if a program address falls within a protected sector, data polling on dq 7 is active for approximately 1 m s, then that bank returns to the read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 100 m s, then the bank returns to read mode. once the embedded algorithm operation is close to being completed, the mbm29dl800ta/ba data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the devices are driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see hardware sequence flags table.) see (6) ac waveforms for data polling during embedded algorithm operations in n timing diagram for the data polling timing specifications and diagrams. dq 6 toggle bit i the mbm29dl800ta/ba also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 2 m s and then stop toggling without the data having changed. in erase, the devices will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 100 s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle. the system can use dq 6 to determine whether a sector is actively erasing or is erase-suspended. when a bank is actively erasing (that is, the embedded erase algorithm is in progress), dq 6 toggles. when a bank enters the erase suspend mode, dq 6 stops toggling. successive read cycles during the erase-suspend-program cause dq 6 to toggle.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 23 to operate toggle bit function properly, ce or oe must be high when bank address is changed. see (7) ac waveforms for toggle bit i during embedded algorithm operations in n timing diagram for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the devices under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in mbm29dl800ta/ba user bus operations tables (byte = v ih and byte = v il ) (in n device bus operation). the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the devices lock out and never complete the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the devices have exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the devices were incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see hardware sequence flags table. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows: for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also hardware sequence flags table and (16) dq 2 vs. dq 6 in n timing diagram. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. to operate toggle bit function properly, ce or oe must be high when bank address is changed.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 24 reading toggle bits dq 6 /dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, this indicates that the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ) . if it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (see (4) toggle bit algorithm in n flow chart) . toggle bit status table *1 : successive reads from the erasing or erase-suspend sector cause dq 2 to toggle. *2 : reading from non-erase suspend sector address indicates logic 1 at the dq 2 bit. ry/by ready/busy the mbm29dl800ta/ba provide a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the devices are busy with either a program or erase operation. if the output is high, the devices are ready to accept any read/ write or erase operation. when the ry/by pin is low, the devices will not accept any additional program or erase commands. if the mbm29dl800ta/ba are placed in an erase suspend mode, the ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth write pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth write pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to (8) ry/by timing diagram during program/erase operations and (9) reset /ry/by timing diagram in n timing diagram for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, the pull-up resistor needs to be connected to v cc ; multiples of devices may be connected to the host system via more than one ry/by pin in parallel. byte/word configuration the byte pin selects the byte (8-bit) mode or word (16-bit) mode for the mbm29dl800ta/ba devices. when this pin is driven high, the devices operate in the word (16-bit) mode. the data is read and programmed at dq 0 mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle* 1 erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1* 2
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 25 to dq 15 . when this pin is driven low, the devices operate in byte (8-bit) mode. under this mode, the dq 15 /a -1 pin becomes the lowest address bit and dq 8 to dq 14 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 0 to dq 7 and the dq 8 to dq 15 bits are ignored. refer to (10) timing diagram for word mode configuration and (11) timing diagram for byte mode configuration and (12) byte timing diagram for write operations in n timing diagram for the timing diagram. data protection the mbm29dl800ta/ba are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the devices automatically reset the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the devices also incorporate several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 2.3 v (typically 2.4 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 2.3 v. if embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up. sector protection device user is able to protect each sector individually to store and protect data. protection circuit voids both program and erase commands that are addressed to protected sectors. any commands to program or erase addressed to protected sector are ignored (see sector protection in n functional description)
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 26 n n n n absolute maximum ratings *1 : voltage is defined on the basis of v ss = gnd = 0 v. *2 : minimum dc voltage on input or i/o pins are C0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods of up to 20 ns. *3 : minimum dc input voltage on a 9 , oe and reset pins is C0.5 v. during voltage transitions, a 9 , o e and reset pins may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in - v cc ) does not exceed + 9.0 v. maximum dc input voltage on a 9 , oe and reset pins is +13.0 v which may overshoot to + 14.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions * : voltage is defined on the basis of v ss = gnd = 0 v. note: operating ranges define those limits between which the functionality of the devices are guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg C55 +125 c ambient temperature with power applied t a C40 +85 c voltage with respect to ground all pins except a 9 , oe , reset * 2 v in , v out C0.5 v cc +0.5 v a 9 , oe , and reset * 1 , * 3 v in C0.5 +13.0 v power supply voltage* 1 v cc C0.5 +5.5 v parameter symbol part no. value unit min max ambient temperature t a ? C40 +85 c power supply voltages* v cc -70 +3.0 +3.6 v -90 +2.7 +3.6 v
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 27 n n n n maximum overshoot/maximum undershoot +0.6 v e0.5 v 20 ns e2.0 v 20 ns 20 ns figure 1 maximum undershoot waveform v cc +0.5 v +2.0 v v cc +2.0 v 20 ns 20 ns 20 ns figure 2 maximum overshoot waveform 1 +13.0 v v cc +0.5 v +14.0 v 20 ns 20 ns 20 ns note : this waveform is applied for a 9 , oe, and reset. figure 3 maximum overshoot waveform 2
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 28 n n n n dc characteristics *1 : the i cc current listed includes both the dc operating current and the frequency dependent component. *2 : i cc active while embedded algorithm (program or erase) is in progress. *3 : this timing is only for sector protection operation and autoselect mode. *4 : applicable for only v cc applying. *5 : automatic sleep mode enables the low power mode when address remain stable for 150 ns. *6 : embedded algorithm (program or erase) is in progress. (@5 mhz) parameter symbol conditions value unit min typ max input leakage current i li v in = v ss to v cc , v cc = v cc max C1.0 ? +1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max C1.0 ? +1.0 m a a 9 , oe , reset inputs leakage current i lit v cc = v cc max a 9 , oe , reset = 12.5 v ? 35 m a v cc active current * 1 i cc1 ce = v il , oe = v ih , f=10 mhz byte ? 18 ma word ? 20 ce = v il , oe = v ih , f=5 mhz byte ? 8 ma word ? 10 v cc active current * 2 i cc2 ce = v il , oe = v ih ? 35 ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v 1 5 m a v cc current (standby, reset) i cc4 v cc = v cc max, reset = v ss 0.3 v 1 5 m a v cc current (automatic sleep mode) * 5 i cc5 v cc = v cc max, ce = v ss 0.3 v, reset = v cc 0.3 v v in = v cc 0.3 v or v ss 0.3 v 1 5a v cc active current * 6 (read-while-program) i cc6 ce = v il , oe = v ih byte ? 45 ma word ? 45 v cc active current * 6 (read-while-erase) i cc7 ce = v il , oe = v ih byte ? 45 ma word ? 45 v cc active current (erase-suspend-program) i cc8 ce = v il , oe = v ih ? 35 ma input low voltage v il C0.5 ? 0.6 v input high voltage v ih 2.0 ? v cc +0.3 v voltage for autoselect and sector protection (a 9 , oe , reset ) * 3, * 4 v id 11.5 12 12.5 v output low voltage v ol i ol = 4.0 ma, v cc = v cc min ? 0.45 v output high voltage v oh1 i oh = C2.0 ma, v cc = v cc min 2.4 ? v v oh2 i oh = C100 m av cc C0.4 ? v low v cc lock-out voltage v lko 2.32.42.5v
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 29 n n n n ac characteristics ? read only operations characteristics note: test conditions: output load: 1ttl gate and 30 pf (mbm29dl800ta/ba-70) 1ttl gate and 100 pf (mbm29dl800ta/ba-90 input rise and fall times: 5 ns input pulse levels: 0.0 v or 3.0 v timing measurement reference level input: 1.5 v output:1.5 v parameter symbols test setup value (note) unit -70 -90 jedec standard min max min max read cycle time t avav t rc 7090ns address to output delay t avqv t acc ce = v il oe = v il 70 90 ns chip enable to output delay t elqv t ce oe = v il 90 90 ns output enable to output delay t glqv t oe 3035ns chip enable to output high-z t ehqz t df 2530ns output enable to output high-z t ghqz t df 2530ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh 00ns reset pin low to read mode t ready 2020 m s ce to b yte switching low or high t elfl t elfh 55ns c l 3.3 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w notes: c l = 30 pf including jig capacitance (mbm29dl800ta/ba-70) c l = 100 pf including jig capacitance (mbm29dl800ta/ba-90) figure 4 test conditions
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 30 ? write/erase/program operations (continued) parameter symbol value unit -70 -90 jedec standard min typ max min typ max write cycle time t avav t wc 70 90 ns address setup time t avwl t as 00ns address setup time to oe low during toggle bit polling t aso 15 15 ns address hold time t wlax t ah 45 45 ns address hold time from ce or oe high during toggle bit polling t aht 00ns data setup time t dvwh t ds 35 45 ns data hold time t whdx t dh 00ns output enable hold time read t oeh 00ns toggle and data polling 10 10 ns ce high during toggle bit polling t ceph 20 20 ns oe high during toggle bit polling t oeph 20 20 ns read recover time before write t ghwl t ghwl 00ns read recover time before write t ghel t ghel 00ns ce setup time t elwl t cs 00ns we setup time t wlel t ws 00ns ce hold time t wheh t ch 00ns we hold time t ehwh t wh 00ns write pulse width t wlwh t wp 35 45 ns ce pulse width t eleh t cp 35 45 ns write pulse width high t whwl t wph 25 25 ns ce pulse width high t ehel t cph 25 25 ns programming operation byte t whwh1 t whwh1 88s word 1616s sector erase operation * 1 t whwh2 t whwh2 11s v cc setup time t vcs 50 50 s rise time to v id * 2 t vidr 500 500 ns voltage transition time * 2 t vlht 44s write pulse width * 2 t wpp 100 100 s oe setup time to we active * 2 t oesp 44s
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 31 (continued) *1 : this does not include the preprogramming time. *2 : this timing is for sector protection operation. parameter symbol value unit -70 -90 jedec standard min typ max min typ max ce setup time to we active * 2 t csp 44s recover time from ry/by t rb 00ns reset pulse width t rp 500 500 ns reset hold time before read t rh 200 200 ns byte switching low to output high-z t flqz 25 30 ns byte switching high to output active t fhqv ? 70 ? 90ns program/erase valid to ry/by delay t busy 90 90 ns delay time from embedded output enable t eoe 70 90 ns
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 32 n erase and programming performance n tsop(1) pin capacitance notes : test conditions t a = + 25c, f = 1.0 mhz dq 15 /a- 1 pin capacitance is stipulated by output capacitance. n fbga pin capacitance notes : test conditions t a = + 25c, f = 1.0 mhz dq 15 /a- 1 pin capacitance is stipulated by output capacitance. parameter limits unit comments min typ max sector erase time 1 10 s excludes programming time prior to erasure word programming time 16 360 m s excludes system-level overhead byte programming time 8 300 m s chip programming time 8.4 25 s excludes system-level overhead program/erase cycle 100,000 cycle parameter symbol test setup value unit typ max input capacitance c in v in = 0 6 7.5 pf output capacitance c out v out = 0 8.5 12 pf control pin capacitance c in2 v in = 0 8 10 pf parameter symbol test setup value unit typ max input capacitance c in v in = 0 6 7.5 pf output capacitance c out v out = 0 8.5 12 pf control pin capacitance c in2 v in = 0 8 10 pf
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 33 n n n n timing diagram ? key to switching waveforms (1) ac waveforms for read operations waveform inputs outputs must be steady may change from h to l may change from l to h h or l any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high- impedance off state we oe ce t acc t df t ce t oe outputs t rc address address stable high-z output valid high-z t oeh t oh
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 34 (2) ac waveforms for hardware reset/read operations (3) alternate we controlled program operations reset t acc t oh outputs t rc address address stable high-z output valid t rh ce t rp t rh t ce t ch t wp t whwh1 t wc t ah ce oe t rc address data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out t df notes: pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode. the addresses differ from 8 mode.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 35 (4) alternate ce controlled program operations t cp t ds t whwh1 t wc t ah we oe address data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd notes: pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 36 (5) ac waveforms chip/sector erase operations * : sa is the sector address for sector erase. addresses = 555h (word) for chip erase. note : these waveforms are for the 16 mode. the addresses differ from 8 mode. v cc ce oe address data t wp we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc 55h 55h 80h aah aah 10h/ 30h 10h for chip erase
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 37 (6) ac waveforms for data polling during embedded algorithm operations t oeh t oe t whwh1 or 2 ce oe t eoe t busy we data t df t ch t ce high-z high-z dq 7 = valid data dq 0 to dq 6 valid data dq 7 * dq 7 dq 0 to dq 6 ry/by data dq 0 to dq 6 = output flag * : dq 7 = valid data (the device has completed the embedded operation).
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 38 (7) ac waveforms for toggle bit i during embedded algorithm operations t dh t oe t ce ce we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph * : dq 6 stops toggling (the device has completed the embedded operation).
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 39 (8) ry/by timing diagram during program/erase operations (9) reset /ry/by timing diagram rising edge of the last we pulse ce ry/by we t busy entire programming or erase operations t rp reset t ready ry/by we t rb
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 40 (10) timing diagram for word mode configuration (11) timing diagram for byte mode configuration (12) byte timing diagram for write operations dq 15 ce byte dq 14 to dq 0 dq 15 /a - 1 t elfh t fhqv t ce a - 1 data output (dq 7 to dq 0 ) data output (dq 14 to dq 0 ) ce byte dq 14 to dq 0 dq 15 /a - 1 t elfl t acc t flqz dq 15 a - 1 data output (dq 14 to dq 0 ) data output (dq 7 to dq 0 ) falling edge of the last we signal ce or we t ah t as input valid byte
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 41 (13) ac waveforms for sector protection t vlht spax a 18 , a 17 , a 16 a 15 , a 14 a 13 , a 12 spay a 0 a 6 a 9 v id v ih t vlht oe v id v ih t vlht t vlht t oesp t wpp t csp we ce t oe 01h data v cc a 1 t vcs spax:sector address for initial sector spay: sector address for next sector note : a -1 is v il on byte mode.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 42 (14) temporary sector unprotection timing diagram (15) bank-to-bank read/write timing diagram v ih reset v cc ce we ry/by t vlht program or erase command sequence t vlht t vcs t vidr v id t vlht unprotection period note dq 2 is read from the erase-suspended sector. ce dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address corresponding of bank 1. ba2: address corresponding of bank 2.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 43 (16) dq 2 vs. dq 6 dq 2 * dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe or ce * : dq 2 is read from the erase-suspended sector.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 44 (17) extended sector protection timing diagram spax : sector address to be protected spay : next sector address to be protected time-out : time-out window = 250 m s (min) spay reset a 6 oe we ce data a 1 v cc a 0 address spax spax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe t wp
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 45 n n n n flow chart (1) embedded program tm algorithm no yes program command sequence (address/command): 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling increment address last address ? program address/program data start programming completed verify data ? no yes embedded program algorithm in program embedded algorithm notes : the sequence is applied for 16 mode. the addresses differ from 8 mode.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 46 (2) embedded erase tm algorithm 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequece (see below) data polling chip erase command sequence (address/command): individual sector/multiple sector erase command sequence (address/command): sector address/30h sector address/30h sector address/30h erasure completed start data = ffh ? no yes embedded erase algorithm in program embedded algorithm notes : the sequence is applied for 16 mode. the addresses differ from 8 mode.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 47 (3) data polling algorithm dq 7 = data? * no no dq 7 = data? dq 5 = 1? yes yes no read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va yes start fail pass * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = byte address for programming = any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = any of the sector addresses within the sector not being protected during chip erase operation
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 48 (4) toggle bit algorithm dq 6 = toggle ? yes no dq 6 = toggle ? dq 5 = 1? yes no no yes read dq 7 to dq 0 twice addr. = va read dq 7 to dq 0 addr. = va start program/erase operation complete program/erase operation not complete. write reset command read dq 7 to dq 0 addr. = va *1 *1, *2 *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to 1. va = bank address being executed embedded algorithm.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 49 (5) sector protection algorithm setup sector addr. (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 ) activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes yes no no oe = v id , a 9 = v id , ce = v il , reset = v ih a 6 = a 0 = v il , a 1 = v ih plscnt = 1 time out 100 m s read from sector addr. = spa, a 1 = v ih , a 6 = a 0 = v il remove v id from a 9 write reset command increment plscnt no yes protect another sector? data = 01h? plscnt = 25? device failed remove v id from a 9 write reset command start sector protection completed () * * : a -1 is v il on byte mode.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 50 (6) temporary sector unprotection algorithm reset = v id *1 perform erase or program operations reset = v ih start temporary sector unprotection completed *2 *1 : all protected sectors are unprotected. *2 : all previously protected sectors are protected once again.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 51 (7) extended sector protection algorithm to sector protection yes no no plscnt = 1 no yes protection other sector start sector protection extended sector plscnt = 25? device failed remove v id from reset completed remove v id from reset write reset command write reset command reset = v id wait to 4 m s protection entry? to setup sector protection write xxxh/60h write spa/60h (a 0 = v il , a 1 = v ih , a 6 = v il ) time out 250 m s to verify sector protection write spa/40h (a 0 = v il , a 1 = v ih , a 6 = v il ) data = 01h? ? device is operating in temporary sector read from sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) increment plscnt setup next sector address no yes yes unprotection mode
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 52 (8) embedded program tm algorithm for fast mode fast mode algorithm start 555h/aah 2aah/55h xxxh/a0h 555h/20h verify data? no program address/program data data polling last address ? programming completed (ba) xxxh/90h xxxh/f0h increment address no yes yes set fast mode in fast program reset fast mode notes : the sequence is applied for 16 mode. the addresses differ from 8 mode.
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 53 n ordering information part no. package access time sector architecture mbm29dl800ta-70pftn mbm29dl800ta-90pftn 48-pin plastic tsop (1) (fpt-48p-m19) (normal bend) 70 90 top sector mbm29dl800ta-70pftr mbm29dl800ta-90pftr 48-pin plastic tsop (1) (fpt-48p-m20) (reverse bend) 70 90 mbm29dl800ta-70pbt mbm29dl800ta-90pbt 48-pin plastic fbga (bga-48p-m12) 70 90 mbm29dl800ba-70pftn MBM29DL800BA-90PFTN 48-pin plastic tsop (1) (fpt-48p-m19) (normal bend) 70 90 bottom sector mbm29dl800ba-70pftr mbm29dl800ba-90pftr 48-pin plastic tsop (1) (fpt-48p-m20) (reverse bend) 70 90 mbm29dl800ba-70pbt mbm29dl800ba-90pbt 48-pin plastic fbga (bga-48p-m12) 70 90 mbm29dl800 t a -70 pftn device number/description mbm29dl800 8mega-bit (1m 8-bit or 512 k 16-bit) cmos flash memory 3.0 v-only read, program, and erase pa c k a g e t y p e pftn = 48-pin thin small outline package (tsop) normal bend pftr = 48-pin thin small outline package (tsop) reverse bend pbt-sf2 =48-ball fine pitch ball grid array package (fbga:bga-48p-m12) speed option see product selector guide. device revision boot code sector architecture t = top sector b = bottom sector
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 54 n nn n package dimensions (contin ued) 48-pin plastic tsop (1) (fpt-48p-m19) note1 : * : values do not include resin protrusion. resin protrusion and gate protrusion are + 0.15 (.006) max (each side) . note2 : pins width and pins thickness include plating thickness. dimensions in mm (inches) 48-pin plastic tsop (1) (fpt-48p-m20) note1 : * : values do not include resin protrusion. resin protrusion and gate protrusion are + 0.15 (.006) max (each side) . note2 : pins width and pins thickness include plating thickness. dimensions in mm (inches) C .003 +.001 C 0.08 +0.03 .007 0.17 "a" (stand off height) 0.10(.004) (mounting height) (.472 .008) 12.00 0.20 * * lead no. 48 25 24 1 (.004 .002) 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 0.10 0.05 (.009 .002) 0.22 0.05 typ 0.50(.020) (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2002 fujitsu limited f48029s-c-5- 6 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part C .003 +.001 .007 C 0.08 +0.03 0.17 "a" (stand off height) (.004 .002) 0.10 0.05 0.10(.004) (mounting height) 12.00 0.20(.472 .008) * * lead no. 48 25 24 1 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 (.009 .002) 0.22 0.05 typ 0.50(.020) (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2002 fujitsu limited f48030s-c-5-6 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 55 (continued) 48-pin plastic fbga (bga-48p-m12) dimensions in mm (inches) c 2001 fujitsu limited b48012s-c-3-3 9.000.20(.354.008) 0.380.10(.015.004) (stand off) (mounting height) 6.000.20 (.236.008) 0.10(.004) 0.80(.031)typ 5.60(.220) 4.00(.157) 48-?0.450.10 (48-?.018.004) m ?0.08(.003) index h g fed c ba 6 5 4 3 2 1 c0.25(.010) .041 C.004 +.006 C0.10 +0.15 1.05
mb m29dl800ta -70/90 /mbm29dl800ba -70/90 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0211 ? fujitsu limited printed in japan

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